1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and in particular, to a semiconductor device manufacturing method of manufacturing a semiconductor device in which a trench-type gate is formed in a semiconductor layer.
2. Description of the Related Art
A trench-type IGBT (Insulated Gate Bipolar Transistor) is known in which a trench is formed in a semiconductor layer formed on a semiconductor substrate, a gate is formed as a result of a polysilicon film being embedded after an oxide film has been formed in the trench, and diffused layers are formed on both sides of the gate.
FIG. 6 shows a sectional view of one example of the trench-type IGBT. In FIG. 6, on a p-type semiconductor substrate 210, a high-concentration n-type epitaxial layer 220 and a low-concentration n-type epitaxial layer 230 are laminated. On the surface of the low-concentration n-type epitaxial layer 230, a p layer 240 is formed. On a surface of the p layer 240, high-concentration n-type diffused layers 250 are formed. A semiconductor layer 260 includes the high-consternation re-type epitaxial layer 220 through the p layer 240 and the high-concentration n-type diffused layers 250. Further, from a surface of the semiconductor layer 260, a trench 270 is formed, and a surface of the trench 270 is covered by an oxide film 280. On the oxide film 280 in the inside of the trench 270, a gate 290 made of polysilicon is formed, and then the top of the gate 290 is covered by the oxide film 280. Further, a collector electrode 205 is formed on a reverse side of the semiconductor substrate 210. Further, emitter electrodes 330 are formed to sandwich both sides of the oxide film 280 provided on the gate 290. Although being omitted from FIG. 6, the emitter electrodes 330 are obtained as a result of contact parts for electric conduction with the high-concentration n-type diffused layers 250 acting as emitters being formed in an interlayer dielectric film formed on a surface of the semiconductor layer 260.
In the above-described IGBT, as a result of a positive voltage being applied to the p layer 240 through the gate 290, an inversion layer (n channel) is formed in the p layer 240. Then, through the inversion layer, an electric current flows from the high-concentration n-type epitaxial layer 220 and the low-concentration n-type epitaxial layer 230 to the high-concentration n-type diffused layers 250. This electric current acts as a base current of a PNP transistor that includes the p-type semiconductor substrate 210, the high-concentration n-type epitaxial layer 220 and low-concentration n-type epitaxial layer 230, and the p layer 240. Thus, an operation of the PNP transistor is carried out in which a collector current flows from the p-type semiconductor substrate 210 to the p layer 240.
In this trench-type IGBT, it is possible to remarkably improve the density of the transistor cells in comparison to a common planar IGBT in which the gate 290 is formed on the surface of the semiconductor layer 260.
Further, as such a trench-type semiconductor device, other than the trench-type IGBT, a trench-type MOS (Metal Oxide Semiconductor) transistor is known and is used as a power MOS transistor.
It is noted that, although being different from the trench-type semiconductor device, such a semiconductor device is known (for example, see Japanese Laid-Open Patent Application No. 2007-207784 (referred to as Patent Document 1, hereinafter)) that in a semiconductor device having a super-junction structure, a thickness of a dielectric film provided on a control electrode in a device part is made equal to or less than one third of a thickness of a dielectric film provided in a terminal part adjacent to the device part.
However, in the above-described trench-type IGBT, an interval between the high-concentration n-type diffused layers 250 as the emitters is reduced in order to increase the density of transistor cells, and as a result, the aspect ratio of the contact parts of the emitter electrodes 330 increases. Thereby, voids may be easily generated above the contact parts in a case where a metal film is formed for the emitter electrodes 330. The aspect ratio means a ratio of the depth of the contact part with respect to the width of the contact part.
FIG. 7 shows in a magnified manner a sectional view of a trench-type IGBT in the related art. In FIG. 7, a trench 270 is formed in a semiconductor layer 260 that includes a low-concentration n-type epitaxial layer 230, a p layer 240 and high-concentration n layers 250 acting as emitters, a gate 290 of polysilicon is formed in the trench 270, and the gate 290 is covered by an oxide film 280. On the oxide film 280, a thermal CVD oxide film 300 and a BPSG dielectric film 310 are laminated, and form an interlayer dielectric film 320. A contact part 330 is formed in the interlayer dielectric film 320, and a metal layer 340 of aluminium is formed on the interlayer dielectric film 320 and is embedded in the contact portion 330.
In this structure, when the pitch of the trenches 270 is reduced, the diameter of the contact part 330 is reduced accordingly. As a result, the aspect ratio of the contact part 330 increases. Thereby, as shown in FIG. 7, a void 370 may be generated at a position of the contact part 330. The void 370 may cause the resistance of the contact part 330 to increase and/or adversely affect the electrode reliability. When the entirety of the interlayer dielectric film 320 is reduced in its thickness to become a thin film in order to solve the problem, then the withstand voltage that is ensured for a guard ring part other than the transistor cell part may be lowered.
Further, Patent Document 1 discloses a semiconductor device. In the semiconductor device, a thick interlayer dielectric film is formed on the entirety of a surface of a semiconductor device having the super-junction structure. After that, all of the interlayer dielectric film is removed for a portion in which the thickness of the interlayer dielectric film is to be reduced. After that, a thin film of a dielectric film is newly formed. However, in this configuration, since all the dielectric film having been formed first is removed from the portion of newly forming the thin film, the number of manufacturing processes increases, and the manufacturing processes may become complicated.